2009 · 10 citations · 13 references
EngineeringComputer EngineeringComputer ScienceReal-time SystemsReal-time Systems ArchitectureReal-time Systems DesignTemporal LogicComponent ArchitectureReal-time Systems ModelingScalabilitySequence DiagramsStatechart ModelingStatechartsTimed AutomataTimed Finite State Machines
Based on a well-defined component architecture the tool supports the synthesis of so-called real-time statecharts from timed sequence diagrams. The two step synthesis process addresses the existing scalability problems by a proper decomposition and allows the user to define particular restrictions on the resulting statecharts.
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Towards the compositional verification of real-time UML designs
Holger Giese, Matthias Tichy, Sven Burmester et al. · 2003 · 149 citations