Design of low jitter PLL for clock generator with supply noise insensitive VCO

Abstract

Supply and substrate noise tend to cause the output clock of PLLs to jitter from their ideal timing. The design of a low jitter PLL has become challenging because of the many design trade-offs between noise and bandwidth. In order to achieve a low jitter PLL design, fully differential signal and control paths of the VCO are maintained. Also, a proposed bandgap regulator helps to achieve high common mode rejection of supply and substrate noise. This proposed bandgap reference serves to reduce oscillator supply and temperature sensitivities and to suppress low/high frequency noise by isolation from supply noise. The simulated oscillator supply noise sensitivity is less than 1 percent/V. Oscillator temperature sensitivity is 500 ppm//spl deg/C in the range of 0 to 100/spl deg/C. Oscillator frequency range is 25 MHz to 400 MHz using a MOSIS 0.8 /spl mu/m CMOS process. The clock skew is less than 60 ps with a peak-to-peak jitter of less than 100 ps for a 200 MHz PLL clock frequency.