A pixel-parallel image processor using logic pitch-matched to dynamic memory

Abstract

A pixel-parallel image processor provides the capability for desktop systems to perform low-level image processing tasks in real time. Compact logic units are pitch-matched to DRAM columns to form dense blocks of processing elements. The processing elements are interconnected to form a 64/spl times/64 array, with each processing element assigned to a single pixel. Operating with a 60-ns clock cycle in a complete system, fully functional devices dissipate 300 mW. Using the devices, low-level image processing tasks have been performed in real time with input images provided at rates exceeding 30 frames/s.