Variable threshold-voltage SOI CMOSFETs with implanted back-gate electrodes for power-managed low-power and high-speed sub-1-V ULSIs

Abstract

An SOI CMOSFET with a variable threshold-voltage (V/sub th/) is proposed for fabricating power-managed low-power and high-speed sub-1-V ULSIs. An experimental SOI CMOS ring-oscillator with 0.7-/spl mu/m-long gates and a variable-Vu, function, fabricated using 0.5-/spl mu/m processes, showed 46% shorter propagation delay than that for bulk CMOSs and 29% shorter delay than that for conventional SOI CMOS under 1-V-operation with almost the same power consumption. These remarkable improvements result from the 0.5-V-lower variable V/sub th/ and larger drain current of the SOI CMOSFET.