A 20MHz BW 68dB DR CT ΔΣ ADC based on a multi-bit time-domain quantizer and feedback element

Abstract

Low-power, small-area, 20MHz-BW ADCs that can be integrated in nanoscale CMOS technologies are of immense interest to the wireless communication industry. Implementation of high-performance analog circuits in nanometric technologies faces several challenges [1]. Time-domain digital signal processing (TDSP) [2] can be used as an alternative for some analog circuits to overcome these challenges. The TDSP technique utilizes the high timing resolution available in nanoscale technologies, and can be implemented using digital circuits that are inherently less susceptible to noise. Circuits using this technique also become faster, smaller and consume less power with technology scaling. Hence, solutions using TDSP with as many digital circuits as possible are desired. An ADC architecture that uses a VCO-based time-domain quantizer is presented in [3]. This architecture uses a conventional feedback element (multi-element DAC with DEM) and 950MHz sample rate that leads to high power consumption. In this work, a pulse-width modulator (PWM) and an all-digital time-to-digital converter (TDC) are used to implement the quantizer as well as the feedback element in the time domain. This approach achieves the necessary linearity in the feedback path without DEM or calibration, and allows a low output rate of 250MS/s.