Hierarchical FPGA Clustering Based on a Multilevel Partitioning Approach to Improve Routability and Reduce Power Dissapation

Abstract

We present a routability-driven top-down clustering technique for area and power reduction in clustered FPGAs. This technique is based on a multilevel partitioning approach. It leads to better device utilization, savings in area, and reduction in power consumption. Routing area reduction of 15% is achieved over previously published results. Power dissipation is reduced by an average of 8.5%