A 3Gb/s/ch transceiver for RC-limited on-chip interconnects

Abstract

A bus-transceiver chip in 0.13 /spl mu/m CMOS uses 10mm uninterrupted differential interconnects of 0.8 /spl mu/m pitch (82MHz RC-limited bandwidth). The chip achieves 3Gb/s/ch using a pulse-width pre-emphasis technique in combination with resistive termination while twisted interconnects mitigate crosstalk. Power consumption is 6mW/ch at a 1.2V supply.