VHDL package for description of fuzzy logic controllers

Abstract

The particular architecture of fuzzy systems has led to the introduction of specific simulators on the market, usually isolated from design environments. This article presents a VHDL package that allows high level descriptions and simulations of fuzzy controllers. The importance of this package to fuzzy hardware design lies not only in its portability to any VHDL simulator but also in that it allows verification of the simulation results of a particular system in a unique and standard simulation environment, from algorithm description level to RTL level (synthesizable) or logic gates. Finally, an example is included to demonstrate the package functionality.