An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects

Abstract

In VLSI interconnect buffers are used to restore the signal level affected by the parasitics. However buffers have a certain switching time that contributes to overall signal delay. Further the transitions that occur in interconnects also contribute to crosstalk delay. Thus the overall delay in interconnects is due to combined effect of both buffer and crosstalk delay. In this work a replacement of buffers with Schmitt trigger is proposed for the same purpose of signal restoration. Due to lower threshold voltage of Schmitt trigger signal can rise early and the large noise margin of Schmitt trigger helps in reducing the noise glitches as well. Simulation results shows that the Schmitt trigger approach gives 20% delay reduction as compared to 10.4% in case of buffers.