A Buck Converter With Reduced Output Spurs Using Asynchronous Frequency Hopping

Abstract

A frequency-hopped buck converter with reduced output spurs in 0.35- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu \hbox{m}$</tex></formula> CMOS is presented. The converter uses pulsewidth-modulation control with eight switching frequencies to achieve 13.2-dB reduction in output spurs from the traditional single-frequency case. The proposed implementation maintains the continuity of the ramp signal, regardless of the frequency selected or when it is selected. Therefore, the hopping rate can be set independently using a clock that is asynchronous to the internal switching frequencies of the converter, and no synchronization between the switching frequencies themselves or between them and the hopping clock is necessary. Moreover, the proposed continuous ramp signal minimizes transients associated with hopping, hence maximizing the hopping rate and spur reduction.