A Quantization Noise Pushing Technique for $\Delta\Sigma$ Fractional-$N$ Frequency Synthesizers

Abstract

This paper demonstrates our proposed quantization noise pushing technique, which moves the quantization noise to higher frequencies and utilizes the low-pass characteristic of the phased-lock loop (PLL) to further suppress the quantization noise. In addition, it can separate the operating frequency of the DeltaSigma modulator and the comparison frequency of the phase/frequency detector (PFD) so as to reduce the loop gain of the PLL and lower the in-band phase noise. This synthesizer was fabricated using the UMC 0.18-mum CMOS process. The chip area measures 0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The supply voltage is 2 V, corresponding to a total power consumption of 26.8 mW. The experimental results show that, with this technique, the in-band phase noise can be lowered by 12 dB, while the out-of-band phase noise can be reduced by more than 15 dB, compared to a synthesizer with the same PFD comparison frequency.