Parallelized Very High Radix Scalable Montgomery Multipliers

Abstract

This paper describes a parallelized very high radix scalable Montgomery multiplier designed for non-redundant FPGA implementations. It improves on the very high radix scalable architecture by using techniques to parallelize the two multiplications within each processing element. The new design can perform 1024-bit modular exponentiation in 5.0 ms and 256- bit modular exponentiation in 0.20 ms using 2593 4-input lookup tables and 32 16 × 16 multipliers, improving the fastest scalable design yet reported.