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An HDTV video coder IC for ATV receivers
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1997
Year
Sdram Memory BandwidthEngineeringMultimedia Signal ProcessingAtv ReceiversVideo Coding FormatComputer EngineeringDigital TelevisionDual Decoder ArchitectureVideo TransmissionSignal Processing
An HDTV video decoder IC for ATV receivers is presented. Its dual decoder architecture supports MPEG-2 MP@HL (62,668,800 display samples per second) and an SDRAM memory bandwidth of 6.5 gigabits per second.