High-Speed CMOS Chip Design for Manchester and Miller Encoder

Abstract

In this paper, we propose a modified Manchester and Miller encoder that can operate in high frequency without a sophisticated circuit structure. Based on the previous proposed architecture, the study has adopted the concept of parallel operation to improve data throughput. In addition, the technique of hardware sharing is adopted in this design to reduce the number of transistors. The study uses TSMC CMOS 0.35-mum 2P4M technology. The simulation result of HSPICE indicates that it functions successfully and works at 200-MHz speed. The average power consumption of the circuit under room temperature is 549 muW. The total core area is 70.7 mumtimes72.2 mum. As expected, the circuit can be easily integrated into radio frequency identification (RFID) application.