Parasitic inductance effect on switching losses for a high frequency Dc-Dc converter

Abstract

This work examines the impact of packaging parasitics on the efficiency of a synchronous DC-DC buck converter. An analytical model of the losses in the converter is developed and this is compared to practical results at switching frequencies in the range of 1-2 MHz. The effect that the packaging parasitic inductance has on efficiency is highlighted by predicting the expected losses from a converter with optimised packaging parasitics.