Fundamenta Informaticae · 2007 · 24 citations · 8 references
ComputingComputer ScienceAlgorithmsFormal MethodsReal-time SystemsAutomata TheoryFinite AutomataFinite State Machine ModelingFinite-state MachinesModel CheckingVerificationAutomata In Formal VerificationReachabilityReachability AnalysisReal-time Systems VerificationSatisfiability ProblemTimed AutomataTimed Automata VerificationTimed Model Checking
Reachability analysis for timed automata using SAT-based methods was considered in many papers, occurring to be a very efficient model checking technique. In this paper we show how to apply this method of verification to timed automata with discrete data, i.e., to standard timed automata augmented with integer variables. The theoretical description is supported by some preliminary experimental results.
8
Rajeev Alur, David L. Dill · Theoretical Computer Science · 1994 · 6.5K citations
Verics: A Tool for Verifying Timed Automata and Estelle Specifications
Piotr Dembiński, Agata Janowska, Paweł Janowski et al. · 2003 · 25 citations