An efficient modeling approach for substrate noise coupling analysis

Abstract

A computationally efficient and accurate substrate noise coupling model for heavily doped CMOS processes is presented and validated with simulations and experimental data. The model is based on Z parameters that are scalable with contact separation and size. This results in fast extraction of substrate resistances for large circuit examples. Several examples demonstrate that this approach can be orders of magnitude faster than currently available techniques for substrate resistance extraction. The computed substrate resistances are within 10% of numerical simulations.