The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis

TLDR

Sizing rules capture technology‑specific design knowledge at the transistor‑pair level. The paper introduces the sizing rules method for basic building blocks in analog CMOS and bipolar circuit design. The method builds a hierarchical library of transistor‑pair groups, derives generic constraint lists to ensure block function and robustness, and implements an automatic recognition procedure for building blocks in circuit schematics. The method reduces effort and improves quality in analog circuit synthesis, as demonstrated by benefits in circuit sizing, design centering, response surface modeling, and analog placement.

Abstract

This paper presents the sizing rules method for basic building blocks in analog CMOS and bipolar circuit design. It consists of the development of a hierarchical library of transistor-pair groups as basic building blocks for analog CMOS and bipolar circuits, the derivation of a hierarchical generic list of constraints that must be satisfied to guarantee the function and robustness of each block, and the development of a reliable automatic recognition procedure of building blocks in a circuit schematic. Sizing rules efficiently capture design knowledge on the technology-specific level of transistor-pair groups. This reduces the effort and improves the resulting quality for analog circuit synthesis. Results of applications like circuit sizing, design centering, response surface modeling, or analog placement show the benefits of the sizing rules method.