Integrated injection logic: a new approach to LSI

TLDR

Multicollector transistors fed by carrier injection are fabricated using a simplified five‑mask bipolar process that achieves a packing density of 400 gates mm⁻² with 5 μm interconnects. The resulting logic achieves a power‑delay product of 0.4 pJ per gate, operates below 1 V, and supports wide current scaling, enabling very low‑power applications and integration with analog circuitry.

Abstract

Multicollector transistors fed by carrier injection are used. A simplified (five masks) standard bipolar process is used resulting in a packing density of 400 gates/mm/SUP 2/ with interconnection widths and spacings of 5 /spl mu/m. The power-delay time product is 0.4 pJ per gate. An additional advantage is a very low supply voltage (less than 1 V). This, combined with the possibility of choosing the current level within several decades enables use in very low-power applications. With a normal seven-mask technology, analog circuitry has been combined with integrated injection logic (I/SUP 2/L).