Device and Architecture Outlook for Beyond CMOS Switches

TLDR

CMOS scaling will ultimately be limited by fundamental constraints, prompting the exploration of non‑charge‑based switches such as spin, excitonic, photonic, magnetic, quantum, and thermal devices, whose intrinsic limits are governed by thermodynamic entropy and Shannon noise. These nanoscale devices transmit tokens via spin, excitonic, photonic, magnetic, quantum, or thermal domains and necessitate new transport mechanisms to replace conventional charge‑based interconnects. Their emergent physical behaviors enable algorithm‑specific architectures that can extend throughput in high‑performance computing.

Abstract

Sooner or later, fundamental limitations destine complementary metal-oxide-semiconductor (CMOS) scaling to a conclusion. A number of unique switches have been proposed as replacements, many of which do not even use electron charge as the state variable. Instead, these nanoscale structures pass tokens in the spin, excitonic, photonic, magnetic, quantum, or even heat domains. Emergent physical behaviors and idiosyncrasies of these novel switches can complement the execution of specific algorithms or workloads by enabling quite unique architectures. Ultimately, exploiting these unusual responses will extend throughput in high-performance computing. Alternative tokens also require new transport mechanisms to replace the conventional chip wire interconnect schemes of charge-based computing. New intrinsic limits to scaling in post-CMOS technologies are likely to be bounded ultimately by thermodynamic entropy and Shannon noise.