A novel powering-down scheme for low Vt CMOS circuits

Abstract

In this paper, a novel powering-down scheme with a virtual power/ground rails clamp (VRC) circuit is proposed. It features the 98% off-leakage current reduction, without the operating speed degradation and the high Vt transistors. The VRC scheme does not need the extra circuits and the timing design for data holding in the sleep mode. This effectiveness has been confirmed by the 24-bit multiplier-accumulator, using 0.25 /spl mu/m CMOS double-layer metal technology.