Four-quadrant CMOS analog multiplier based on new current squarer circuit with high-speed

Abstract

In this paper a new CMOS current-mode four-quadrant analog multiplier circuit based on squarer circuit is proposed. The dual translinear loop is the basic building block in realization scheme. Supply voltage is 3.3 V. The major advantages of this multiplier are high speed, low power, high linearity and less dc offset error. The circuit is designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 mum standard CMOS technology. The simulation results of analog multiplier demonstrate a linearity error of 1.15%, a THD of 0.76% in 1 MHz, a -3 dB bandwidth of 44.9 MHz and a maximum power consumption of 0.24 mW.