An universal input and output RNS converter

Abstract

A systolic architecture is presented which is capable of both input and output conversion with a throughput equal to that of the fast residue number system (RNS) processes of addition and multiplication. The converter can be used with an arbitrary RNS (within certain realization-imposed limits). An actual anticipated VLSI layout is described that will be programmable for RNSs with up to eight moduli of six bits or less. This should provide an off-the-shelf solution for many RNS conversion requirements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>