Low-power class-AB CMOS OTA with high slew-rate

Abstract

In this paper, a novel low-power class-AB CMOS OTA with high slew-rate is presented. The proposed OTA is based on class-AB input stage using a novel adaptive-biasing. The proposed OTA designed using a standard 0.18-um CMOS technology indicates that rising and falling slew-rates of +4.92 V/¿S and -5.04 V/¿S with worst-case settling time of 2.1 ¿S, a voltage gain of 48.97 dB with GBW of 57.27 kHz and phase margin of 78.18 degree were achieved with 10-pF load capacitance and 1.8-V supply voltage. The proposed OTA consumes an overall current of 1.09 ¿A, and occupies a silicon area of 0.008 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .