A Novel Topology Based on Forward Converter with Passive Power Factor Correction

Abstract

A new topology of the forward converter with passive power factor correction is proposed. The degree of novelty consists by adding the third winding of the forward converter in the valley fill circuit. In this way, a forward converter with high power factor and lower THD can be obtained. This is a good solution for low and medium power application. The paper describes the proposed circuit. An important advantage of this circuit is that the maximum voltage on power transistor will be reduced from 2 U <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</sub> to about 1.5 U <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</sub> .