Design of a CMOS floating-gate resistor for highly linear amplifier and multiplier applications

Abstract

We present implementations of highly linear amplifier and multiplier circuits that employ a linear CMOS resistor. This tunable resistor is built by utilizing the common-mode linearization technique, and by exploiting the gate-coupling and charge-storage characteristics of the floating-gate transistors. It exhibits 0.01% THD for 1V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp </sub> input. Also, the amplifier has an input linear range of 2.5V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> for differential and single-ended inputs, and achieves 0.018% THD for 1V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">pp</sub> differential input