Publication | Closed Access
On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation
65
Citations
3
References
2002
Year
Unknown Venue
On-chip Inductance Modeling3D Ic ArchitectureElectrical EngineeringPhysical Design (Electronics)EngineeringVlsi DesignLayout DesignVlsi ArchitectureRlc ExtractionAccurate Inductance EstimationComputer EngineeringVlsi InterconnectsPower ElectronicsElectronic PackagingMicroelectronicsInterconnect (Integrated Circuits)Circuit Simulation
On-chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and ground inductive noise.
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