IEEE Micro · 1996 · 23 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureEmbedded SystemsSystem-on-chip DesignData CompressionEmbedded Memory BlocksImage CompressionMemory Hierarchy DesignMemory Subsystem DesignSource CodingEmbedded Memory IntegrationHierarchical Memory ArchitectureOn-chip Memory DesignPipeline ArchitectureReal-time ProcessingRisc ArchitecturesRisc-v Core DesignVideo Compression
Our two-chip, real time, MPEG-2, simple-profile-at-main-level encoder supports NTSC 4:2:0 video signals with only three external memories. We have developed a compact encoder chip set. The key features of this chip set are a low encoding delay based on a simple profile at main level; wide-range motion estimation, which it performs using a hierarchical search; a flexible, macroblock level pipeline architecture based on RISC CPUs; and three small peripherals with no glue logic: a VRAM, synchronous DRAM, and FIFO DRAM.
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A single-chip MPEG2 video decoder LSI
T. Demura, T. Oto, K. Kitagaki et al. · 2002 · 40 citations
A motion estimation processor for MPEG2 video real time encoding at wide search range
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A chip set architecture for programmable real-time MPEG2 video encoder
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