VLSI implementation of MIMO detection using the sphere decoding algorithm

TLDR

Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high‑rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The ASICs achieve high throughput and low complexity through depth‑first tree traversal with radius reduction, a one‑node‑per‑cycle architecture, use of the infinity norm instead of the squared norm, and efficient enumeration. The first ASIC attains maximum‑likelihood performance with an average throughput of 73 Mb/s at 20 dB SNR, while the second shows negligible bit‑error‑rate degradation and achieves 170 Mb/s at the same SNR, ranking among the fastest reported MIMO detector implementations.

Abstract

Multiple-input multiple-output (MIMO) techniques are a key enabling technology for high-rate wireless communications. This paper discusses two ASIC implementations of MIMO sphere decoders. The first ASIC attains maximum-likelihood performance with an average throughput of 73 Mb/s at a signal-to-noise ratio (SNR) of 20 dB; the second ASIC shows only a negligible bit-error-rate degradation and achieves a throughput of 170 Mb/s at the same SNR. The three key contributing factors to high throughput and low complexity are: depth-first tree traversal with radius reduction, implemented in a one-node-per-cycle architecture, the use of the /spl lscr//sup /spl infin//-instead of /spl lscr//sup 2/-norm, and, finally, the efficient implementation of the enumeration approach recently proposed in . The resulting ASICs currently rank among the fastest reported MIMO detector implementations.