An open-loop full CMOS 103 MHz -61 dB THD S/H circuit

Abstract

Based on a real open loop architecture and a cascode-driver CMOS source-follower, we implemented a S/H circuit in a 0.8 /spl mu/m digital CMOS process. The circuit achieved -61 dB THD at a sampling rate of 103 MHz, while a 1.42 V/sub p-p/ 10 MHz input signal was applied. This includes all parasitic loading and transient effects.