CMOS implementation of a current conveyor-based field-programmable analog array

Abstract

To date, all published CMOS field-programmable analog array (FPAA) designs have operated under 1 MHz bandwidths. This paper develops circuit methods allowing the development of a CMOS FPAA operating at greater than 1 MHz frequencies. For this purpose the second-generation current conveyor (CCII) is used. IC test results of a 0.8 /spl mu/m CMOS chip containing four configurable analog blocks (CABs) based on the CCII, as well as an interconnection network based on transmission gates, are presented. The rest results show that bandwidths exceed 10 MHz. The four CABs and interconnect occupy a core area of 1551.8/spl times/74.1 /spl mu/m/sup 2/.