A unified approach to the approximate symbolic analysis of large analog integrated circuits

TLDR

The paper proposes a unified method for approximate symbolic analysis of large linearized analog circuits in the complex frequency domain. It combines two novel approximation strategies—generating magnitude‑ordered common trees via color‑constrained spanning trees and sensitivity‑based simplification of two‑graphs—to reduce tree enumeration complexity. The approach enables accurate symbolic analysis of circuits with up to 39 transistors, far exceeding previous limits of fewer than 15, though scalability is ultimately constrained by the interpretability of the resulting symbolic functions.

Abstract

This paper describes a unified approach to the approximate symbolic analysis of large linearized analog circuits in the complex frequency domain. It combines two new approximation-during-computation strategies with a variation of the classical two-graph tree enumeration method. The first strategy is to generate common trees of the two-graphs, and therefore the product terms in the symbolic network function, in the decreasing order of magnitude. This is made possible by our algorithm for generating color-constrained spanning trees in the order of weight. It avoids the burden of computing all the product terms only to find most of them numerically negligible. The second approximation strategy is the sensitivity-based simplification of two-graphs, which excludes from the two-graphs many of the insignificant circuit elements that have little effect on the network function being derived. It significantly reduces the complexity of the two-graphs before tree enumeration. Our approach is therefore able to symbolically analyze much larger analog integrated circuits than previously reported, using complete small signal models for the semiconductor devices. We show accurate yet reasonably sized symbolic network functions for integrated circuits with up to 39 transistors whereas previous approaches were limited to less than 15. For even larger circuits, the limit is imposed mainly by the interpretability of the generated symbolic network function.