The MPEG-4 video coding standard-a VLSI point of view

TLDR

The paper reviews the current status of the MPEG‑4 video coding standard and discusses its practical implementation potential and challenges. The authors propose a VLSI architecture that partitions the standard into stream, video, and composition processors, each programmable yet tailored to the typical requirements of its algorithm class. Complexity analysis shows that real‑time MPEG‑4 decoding would exceed the processing limits of even future high‑performance microprocessors, yet the standard still offers sufficient design space for an optimized, low‑cost, low‑power implementation.

Abstract

The paper presents an overview of the current status of the emerging MPEG-4 video coding standard and a discussion of the potential and problems for a practical implementation. Though the high flexibility of the standard suggests a software implementation on microprocessors or DSP, a complexity analysis of the standard proved, that the required processing power for a real time codec implementation quickly reaches the limits even of future high-performance microprocessors. But even with its high number of different algorithms, the standard leaves enough design space for a successful implementation as an optimised, but flexible low-cost, low-power solution. By identifying common arithmetic and transfer properties of the algorithms involved, a partitioning into a stream, video, and composition processor is proposed. Each of the units is programmable, but dedicated to the typical requirements of each algorithm class.