A means of reducing custom LSI interconnection requirements

Abstract

Large-scale integrated circuit interconnect approaches such as pad relocation and discretionary techniques have been developed for interconnecting very large numbers of circuits on monolithic integrated-circuit wafers. Although these approaches were perhaps premature in their original development, considerable interest is currently being shown in full wafer LSI. In order to avoid the defective circuits that naturally occur on such large circuit arrays, it has been necessary to customize each wafer's interconnection mask to its unique yield pattern. The authors examine in detail a means of using each mask set for perhaps several unique wafers, thus providing important custom routing and mask generation cost savings. In the case of pad relocation, only a single mask then comprises the entire custom mask set for several wafer arrays.