A low-power, low noise, configurable self-timed DSP

Abstract

This paper describes a commercial implementation of a self-timed DSP. The self-timed design is fully compatible with a synchronous implementation allowing comparisons of both design styles to be made. The self-timed implementation has shown many benefits over its synchronous counterpart especially with regards power consumption and noise emissions. It also demonstrates the commercial viability of self-timed designs in power and noise sensitive applications. This paper also introduces the concept of a highly configurable Application Specific Integrated Architecture (ASIA/sup TM/).