A 7.1-mW 1-GS/s ADC with 48-dB SNDR at Nyquist rate

Concepts

EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsAnalog Integrated CircuitsCmos Circuit DesignDigital Integrated Circuit DesignDigital Integrated CircuitsDigital Signal ProcessingMixed-signal Integrated Circuit DesignAnalog Amplifier DesignAnalog-digital ConversionAnalog-to-digital ConversionAnalog-to-digital Converter DesignAnalog-to-digital ConvertersCmos Analog Circuit DesignCmos Analog Integrated CircuitsDigital-to-analog Converters

Abstract

A two-stage pipelined ADC employs a double-sampling residue amplifier, two interleaved precharged DACs, and a new calibration scheme to correct for residue gain error, offset, and nonlinearity. Realized in 65-nm CMOS technology and sampling at 1 GHz, the prototype exhibits an FOM of 25 fJ/conversion-step while drawing 7.1 mW from a 1-V supply.

References

A 150 MS/s 133$~\mu$W 7 bit ADC in 90 nm Digital CMOS

Geert Van der Plas, Bob Verbruggen · IEEE Journal of Solid-State Circuits · 2008 · 71 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS

Bob Verbruggen, Jan Craninckx, Maarten Kuijk et al. · 2010 · 58 citations

Engineering, Computer Engineering, Electrical Engineering +17

A 10-bit 1-GHz 33-mW CMOS ADC

Bibhu Datta Sahoo, Behzad Razavi · 2012 · 22 citations

Engineering, Electrical Engineering, Analog Electronics +13