IEEE Journal of Solid-State Circuits · 2009 · 309 citations · 22 references
EngineeringElectrical EngineeringLow-power DesignMicroelectronicsWireless CommunicationsCmos Circuit DesignMicrowave OscillatorsRadio-frequency Integrated CircuitsReceiver SystemsRf MemsWireless Sensor NetworksCmos Radio-frequency CircuitsDuty Cycle ControlLow-power Cmos DesignNetwork Latency ReductionPower ConsumptionReceiver DesignReceiver SensitivitySensor Nodes
A dedicated wake-up receiver may be used in wireless sensor nodes to control duty cycle and reduce network latency. However, its power dissipation must be extremely low to minimize the power consumption of the overall link. This paper describes the design of a 2 GHz receiver using a novel ldquouncertain-IFrdquo architecture, which combines MEMS-based high-Q filtering and a free-running CMOS ring oscillator as the RF LO. The receiver prototype, implemented in 90 nm CMOS technology, achieves a sensitivity of -72 dBm at 100 kbps (10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> bit error rate) while consuming just 52 muW from the 0.5 V supply.
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