Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technology

Abstract

This paper proposes a sub-1V, robust and compact SRAM cell in double gate MOS (DGMOS) technology. The presented SRAM cell is a six transistors cell characterized by two word lines connected to the front and back gate of each access transistors, respectively. Simulations, using a 32nm low operating power DGMOS predictive model, show excellent read/write cell stability at minimal transistor dimension. Thanks to the excellent cell stability, the proposed 6T-2WL cell is also a good candidate for low voltage applications.