Performance of sorting algorithms on the SRC 6 reconfigurable computer

Abstract

The execution speed of the FPGA processing elements are compared to the microprocessor processing elements in the SRC 6 reconfigurable computer using the following algorithms for sorting: quick sort, heap sort, radix sort, bitonic sort, and odd/even merge. The results show that, for sorting, FPGA technology may not be the best processor choice and that factors such as memory bandwidth, clock speed, algorithm computational density and an algorithm's ability to be pipelined all have an impact on FPGA performance.