A Study of the Error Behavior of a 32-bit RISC Subjected to Simulated Transient Fault Injection

Abstract

In this paper; a simulation-based fault injection technique is used to study various aspects of the error behavior of a 32bit pipelined RISC, using a register level model written in VHDL. Consequences on the error behavior owing to the fault location were studied speciJcally. Finally, the efJiciency of two built-in error-detecting methods was evaluated