IEEE Journal of Solid-State Circuits · 2006 · 81 citations · 10 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesAnalog Integrated CircuitsCmos Circuit DesignDigital Image ProcessingImage ProcessingLow-noise Circuit DesignLow-power Digital Circuit DesignCmos Digital Circuit DesignEnergy-efficient Digital CircuitsImager DesignLow-power Circuit DesignLow-power Cmos DesignLow-voltage Cmos DesignPower ConsumptionPower Consumption Optimization
This paper presents a CMOS imager with column-level ADC that uses a dynamic column fixed-pattern noise (FPN) reduction technique. This technique, called dynamic column switching (DCS), strongly reduces the perceptual effects of nonuniformities introduced by the column-level ADC or any other column-wise circuit element. This relaxes the uniformity requirements on the column-level ADC circuitry, which can significantly decrease power consumption and chip area. The proposed DCS technique requires only five transistors per column and minimal digital overhead at the chip level. A prototype was realized in a 0.18 mum CMOS process. The implemented column-level ADC uses a single-slope architecture and features a low-power column circuit design. In the measured images, the application of dynamic column switching make a column FPN of plusmn0.67% of full scale nearly invisible to the human eye
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Abbas El Gamal, Helmy Eltoukhy · IEEE Circuits and Devices Magazine · 2005 · 783 citations
A 60 mW 10 b CMOS image sensor with column-to-column FPN reduction
Tadashi Sugiki, Shinji Ohsawa, Mamoru Sasaki et al. · 2002 · 67 citations
A single-chip 306×244-pixel CMOS NTSC video camera
S.G. Smith, Jed Hurwitz, M. Torrie et al. · 2002 · 43 citations
An integrated 800×600 CMOS imaging system
Woodward Yang, Oh-Bong Kwon, Ju-Il Lee et al. · 2003 · 41 citations
Engineering, Computer Engineering, Electrical Engineering +17