Minimum area cost for a 30 to 70 Gbits/s AES processor

Abstract

This paper presents the design decisions and area optimizations to obtain a high throughput, over 30 Gbits/s AES processor. With loop unrolling and outer-round pipelining techniques, throughputs of 30 Gbits/s to 70 Gbits/s are achievable in a 0.18 /spl mu/m CMOS technology. Moreover, by using inner round pipelining of the composite field implementation of the substitution phase and designing an offline key scheduling unit for the AES processor the area cost is reduced by 48% while the same throughput is maintained. Therefore, the over 30 Gbits/s, fully pipelined AES processor operating in the counter mode can be use for the encryption of data on optical links.