A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

Abstract

In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40'' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.