Synthesis Method for Hierarchical Interface-Based Supervisory Control

Abstract

Hierarchical interface-based supervisory control (HISC) decomposes a discrete-event system (DES) into a high-level subsystem which communicates with n ges 1 low-level subsystems, through separate interfaces. It provides a set of local conditions that can be used to verify global conditions such as nonblocking and controllability such that the complete system model never needs to be constructed. Currently, a designer must create the supervisors himself and then verify that they satisfy the HISC conditions. In this paper, we develop a synthesis method that can take advantage of the HISC structure. We replace the supervisor for each level by a corresponding specification DES. We then construct for each level a maximally permissive supervisor that satisfies the corresponding HISC conditions. However, the method does not guarantee global maximal permissiveness, only level-wise maximal permissiveness. We define a set of language-based fixpoint operators and show that they compute the required level-wise supremal languages. We then discuss the complexity of our algorithms and show that they potentially offer significant savings over the monolithic approach. We also briefly discuss a symbolic HISC verification and synthesis method using binary decision diagrams, that we have also developed. A large manufacturing system example (worst-case statespace on the order of 1030) extended from the AIP example is briefly discussed. The example showed that we can now handle a given level with a statespace as large as 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> states, using less than 160 MB of memory. This represents a significant improvement in the size of systems that can be handled by the HISC approach. A software tool for synthesis and verification of HISC systems using our approach was also developed.