A 100 K gate sub-micron BiCMOS gate array

Abstract

A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%. A description is given of the chip architecture and the implementation of a dual-cascode digital filter (74 K gates) with testability features such as JTAG and two-phase scan