An efficient back-bias generator with hybrid pumping circuit for 1.5 V DRAMs

Abstract

The authors propose an efficient back-bias voltage (Vbb) generator with a newly introduced hybrid pumping circuit (HPC). This hybrid system uses one NMOS pumping transistor and one PMOS pumping transistor and can pump as low as the -Vcc level without a Vth loss. By adopting a triple-well structure at the pumping circuit area, the NMOS transistor can be employed as a pumping transistor without minority carrier injection.