High efficiency power amplifier input/output circuit topologies for base station and WLAN applications

Abstract

The design and measured results of Class-F output and input circuits for high efficiency operation of power amplifiers is presented. With the circuits presented in this paper, drain efficiencies of 85% can be obtained if the 2/sup nd/ and 3/sup rd/ harmonics are controlled. Efficiencies rise to 95% if the 4/sup th/ and 5/sup th/ harmonics are also controlled. A Class-F input circuit proposed to overcome the negative effects on PAE and efficiency caused by input capacitance variation. By shaping the input waveform the Class-F circuit creates a 50% duty cycle which prevents excessive power dissipation on the gate resistance, hence preventing gain and PAE degradation. A 15 W power amplifier designed at 1.8 GHz was fabricated to validate the presented techniques. The amplifier was designed utilising a FCSL (Filtronic Compound Semiconductors Ltd.) pHEMT device with a total gate periphery of 24 mm. With an unmodulated carrier, 16 watts of output power at 76% drain efficiency and 16 dB small-signal gain was obtained. The amplifier delivered 5.2 watts with a PAE of 48% under EDGE modulation.