A low-power 12-b analog-to-digital converter with on-chip precision trimming

Abstract

The design and performance of a 12-b charge redistribution analog-to-digital converter (ADC) is described. The architecture is chosen to minimize power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a 1- mu m CMOS process. It converts at a 200-kHz rate with a power dissipation of 10 mW.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>