A one-million-circuit CMOS ASIC logic family

Abstract

Metallization and device channel length enhancements to an existing 0.5-/spl mu/m CMOS process are exploited in the design of a high-density ASIC (application-specific integrated circuit) logic family. Wired circuit density exceeds one-million equivalent two-input NANDs, with typical gate delays of 250 ps at 3.3 V. A total of 17 different chip sizes are offered, along with several surface-mount package options. Both IBM and industry-standard design systems are supported, along with a cost effective LSSD-based test methodology.