A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADC

Abstract

A 1.2V 6b 1GS/s ADC is fabricated in a 90nm CMOS process, occupies 0.13mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and consumes 55mW. This ADC uses background offset-calibration to enable the use of minimum-size devices in pre-amplifiers and comparators. A solution that guarantees fast selection of the important reference voltages, and halves the number of switches in the resistor ladder, further improves high-frequency performance